OBIRCH Fault Localization Analysis: A Comprehensive Technical Guide

OBIRCH (Optical Beam Induced Resistance Change) fault localization analysis is a powerful laser-based technique widely used in semiconductor failure analysis to precisely identify resistive defects, shorts, and leakage sites in integrated circuits. This non-destructive method enables both front-side and backside inspection, making it indispensable for advanced IC packaging and process node failure analysis. In this article, we explore the principles, testing methodology, sample requirements, and practical applications of OBIRCH fault localization.

Technical Overview

OBIRCH (Optical Beam Induced Resistance Change) is a laser scanning microscopy technique used to localize electrical faults in semiconductor devices by detecting localized resistance changes induced by thermal excitation. During analysis, a focused laser beam scans across the surface of a powered device. When the laser strikes a defective region—such as a short circuit, abnormal via, or resistive junction—the localized heating causes a measurable change in the current or voltage of the device under test (DUT). This change is captured and mapped as a bright spot on the laser-scanned image, revealing the exact physical location of the defect.

The fundamental mechanism behind OBIRCH is the temperature coefficient of resistance (TCR) of the materials involved. When the laser beam heats a conductive path, the resistance of that path changes proportionally to its TCR. In a healthy circuit, the induced change is uniform and predictable. However, at defect sites such as metal bridging, junction leakage, or abnormal contacts, the local resistance responds anomalously to the thermal stimulus, producing a distinctive signal contrast that pinpoints the fault location with micrometer-level precision.

OBIRCH is frequently used as a complementary technique to EMMI (Emission Microscopy) and Thermal Laser Stimulation methods such as TIVA and OBIRCH-LOCKIN. While EMMI is highly effective for detecting forward-biased junction leakage and hot carrier emission, OBIRCH excels at identifying resistive shorts, backside defects, and failures that do not emit visible photons. Together, these methods form a comprehensive fault localization workflow in modern failure analysis laboratories.

Testing Samples

Bare Dies and Wafers

Unpackaged dies and wafer-level samples can be analyzed directly, provided that electrical contact can be established through probe needles or a dedicated test fixture. Front-side analysis is typically performed on devices with minimal passivation interference, while backside analysis requires silicon substrate thinning to approximately 100–200 micrometers to ensure sufficient laser penetration at the 1340 nm wavelength commonly used for backside OBIRCH.

Packaged Integrated Circuits

Fully packaged devices in QFP, QFN, SOP, BGA, and CSP formats are among the most common samples for OBIRCH analysis. For backside analysis, the package molding compound and silicon substrate must be progressively ground and polished to achieve the required transparency to the infrared laser. This preparation preserves the electrical integrity of the device while enabling deep fault localization through the silicon substrate.

PCBA and System-Level Assemblies

Board-level failures involving individual ICs can also be investigated, provided the failing component can be electrically stimulated in a stable failure state. In such cases, the component is typically decapsulated or delidded to expose the die surface for laser scanning.

Sample Preparation Requirements

• The sample must exhibit a stable and reproducible electrical failure signature during testing.
• Backside samples require substrate thinning to 100–200 µm with a mirror-polished finish to minimize laser scattering.
• Front-side samples should have passivation layers thinner than 2 µm for 1340 nm laser penetration.
• The electrical biasing condition (constant current or constant voltage) must be defined based on the failure mode.
• Samples must be free of surface contamination, oxidation, and residual molding compound after preparation.

Testing Items

OBIRCH fault localization analysis covers a wide range of electrical failure modes and defect types in integrated circuits:

• Interconnect shorts and metal bridging between adjacent lines or layers.
• High-resistance vias, contacts, and through-silicon vias (TSVs) in advanced packaging.
• Gate oxide defects and pinholes causing leakage paths.
• Junction leakage and P-N junction abnormalities.
• ESD damage sites and latch-up locations.
• Solder joint and bump resistance anomalies in flip-chip devices.
• Poly-silicon filament shorts and silicide defects.
• Leakage current localization in standby or low-power failure modes.
• Dielectric breakdown sites in capacitors and isolation structures.

Testing Methods

Constant Voltage OBIRCH Mode

In constant voltage mode, a fixed voltage is applied across the failing terminals while the laser scans the die. Any resistance change at the defect site modulates the current flowing through the device. This current variation is amplified by a lock-in amplifier synchronized with the laser modulation frequency, allowing detection of signal changes in the nanoampere range. Constant voltage mode is particularly suitable for failures exhibiting low-resistance shorts.

Constant Current OBIRCH Mode

In constant current mode, a fixed current is forced through the device, and the laser-induced resistance change manifests as a voltage variation across the terminals. This mode is advantageous for high-impedance failures and leakage paths where voltage sensing provides better signal-to-noise ratio. The choice between the two modes depends on the I-V characteristics of the failure and the required sensitivity.

Backside Analysis Procedure

For flip-chip packages and devices with dense front-side metallization, backside OBIRCH is the preferred approach. The procedure involves mechanical grinding of the silicon substrate to a uniform thickness, followed by fine polishing. A 1340 nm infrared laser is then used to scan through the thinned substrate, since silicon is transparent at this wavelength. The induced resistance changes are mapped onto a reflected laser image to precisely locate the fault, after which physical analysis methods such as FIB cross-sectioning or SEM inspection confirm the root cause.

Complementary Workflow Integration

• Perform preliminary electrical characterization and curve tracing to confirm the failure mode.
• Select the appropriate biasing condition and laser wavelength based on sample preparation.
• Acquire the reflected laser image and the OBIRCH signal map simultaneously.
• Overlay the fault signature on the device layout database (GDS) for circuit-to-layout correlation.
• Mark the defect coordinates for subsequent physical failure analysis, such as FIB, SEM, TEM, or EDX.

Applications

OBIRCH fault localization analysis serves critical roles across the semiconductor value chain:

• Wafer Fab Failure Analysis: Identifying process-induced defects such as metal stringers, contact silicide anomalies, and gate oxide breakdown to drive yield improvement.
• Package and Assembly Analysis: Localizing bump, bond wire, and substrate interconnect failures in advanced packaging including flip-chip, WLCSP, and 2.5D/3D architectures.
• Quality and Reliability Engineering: Analyzing failures after ESD testing, latch-up testing, temperature cycling, HTOL, and other reliability stress screening.
• New Product Introduction: Supporting debug of first silicon by localizing functional and parametric failures for design and process optimization.
• Customer Return Analysis: Determining root cause of field failures to close the loop between failure signature and manufacturing origin.
• Memory and Logic Devices: Detecting bit-line and word-line shorts in DRAM and NAND, as well as core logic leakage in advanced node SoCs.

FAQ

Q1: What is the difference between OBIRCH and EMMI?

A: OBIRCH detects resistance changes induced by localized laser heating and is best suited for shorts, resistive vias, and backside defects. EMMI detects photon emission from carrier recombination and avalanche effects, making it ideal for junction leakage and hot carrier effects. The two techniques are complementary and are often applied sequentially in a comprehensive failure analysis flow.

Q2: Can OBIRCH be performed on fully packaged devices?

A: Yes. Packaged devices can be analyzed from the backside after proper thinning of the molding compound and silicon substrate. Backside OBIRCH is particularly valuable for flip-chip and BGA packages where front-side access is obstructed.

Q3: What types of defects are best detected by OBIRCH?

A: OBIRCH is most effective for resistive faults, including metal-to-metal shorts, high-resistance vias and contacts, junction leakage, gate oxide pinholes, and ESD-induced damage. It is less effective for fully open circuits, which are better addressed by techniques such as LVI (Light-Induced Voltage Alteration) or opens-type analysis.

Q4: How thick should the silicon substrate be for backside OBIRCH?

A: A typical target thickness is 100–200 micrometers. Thinning improves laser transmission at the 1340 nm wavelength and enhances signal strength, but excessive thinning risks mechanical damage or electrical degradation of the device.

Q5: What follow-up analysis is recommended after OBIRCH localization?

A: Once the fault coordinates are identified and correlated with the layout database, physical analysis such as FIB cross-sectioning, SEM, TEM, or EDX is performed to characterize the defect structure and determine the root cause. This completes the transition from fault isolation to root cause identification.

Q6: Does OBIRCH damage the sample?

A: OBIRCH is considered a non-destructive technique. The laser power is carefully controlled to provide localized heating without causing permanent material modification, allowing the same sample to undergo subsequent physical analysis.